FPGA Horizons logo
FPGA Horizons

LONDON 26

October 6th – 7th 2026

Pullman London St Pancras, Euston Road, London NW1

Exchanging ideas
The demo floor
The demo floor
Chatting with beers

As it happened…

2
days

450
attendees

45
exhibitors

23
talks & workshops

This year FPGA Horizons ran across two days, with Technical Talks and Demos on Day 1, and hands-on Workshops by key industry experts on Day 2. With 45 exhibiting partners, plus larger talk and demo spaces, this turned out to be a must-attend event.

But FPGA Horizons isn’t just about the talks and demos. When asked what they enjoyed most about the event, many of our attendees told us it was the people. It’s a great way to catch up with friends, meet and exchange ideas with new peers, learn from experts and find out more about where the industry is going. And 100% of them said they would attend again.

Here’s what some of you said…

(Click to enlarge)

Thank you to every attendee, speaker, exhibitor and partner. See you next year.

Session Highlights

Tuesday (Day 1)

Keynote

AMD logo
Kirk Saban

System-Level Design Meets AI-Driven Workflows in Modern FPGA Embedded Systems

Kirk Saban, CVP – Embedded Products, Software & Solutions

Designing embedded applications demands an evolving system-level perspective, where workloads are aligned to the right compute architecture and design flows are optimized for faster, higher-quality implementation. This keynote takes a top-down view of modern design, spanning FPGA flexibility, embedded processing, and heterogeneous compute, while examining how advances in AI-driven tools are reshaping FPGA workflows through co-pilot-style interaction for design and verification. Together, these trends are enabling architects and FPGA designers to move from concept to implementation with greater speed and confidence. This session will explore what that means in practice.

Efinix logo
Harald Werner

Leading Low Power, High Speed Small Form Factor System Devices

Harald Werner, VP Sales EMEA and Managing Director EMEA

Efinix offers FPGAs in a small form factor that can serve as system controllers, ideally suited for demanding edge applications. The new System in Package (SiP) devices further simplify integration by combining multiple advantages such as lower power consumption, a smaller footprint, and easier PCB integration. Examples include the Ti125 SIP with integrated HyperRAM and the Ti135 SIP with integrated LPDDR4. These devices deliver unprecedented performance in terms of speed and power efficiency. This presentation provides a detailed overview of the new devices and their features, along with exemplary applications.

Lattice logo
Matt Holdsworth

Practical Security Fundamentals for FPGA Engineers

Matt Holdsworth, Senior FAE

Security is increasingly becoming a core design requirement, even for engineers who do not specialize in it. This session introduces the essential security concepts; trust, privacy, integrity, and availability, in a way that connects directly to FPGA development and real‑world system architecture. Instead of focusing on cryptography or abstract theory, we look at how these principles influence system design and device selection. Attendees will gain a practical understanding of how security requirements will impact their own designs and how hardware‑based security can significantly strengthen the resilience of FPGA‑centric systems.

Altera logo
Graham McKenzie

FPGA Security Demystified

Graham McKenzie, Principal Field Application Engineer

With the emergence of the Cyber Resilience Act and other industry inflection points, design security is becoming more important and certainly more talked about. But what is design security, what features are available in FPGAs and how do they help secure my design and my product?

During this talk, we will explore the fundamentals of design security, examine how security features have evolved, and discuss how Altera is prepared for a post-quantum world. We will review specific FPGA security features, the threats they mitigate, and how they are implemented, so that security becomes less of a mystery and more of routine aspect of FPGA engineering.

Microchip logo
Ian Pearson

The Cyber Resilience Act is Here: Are Your FPGAs Ready?

Ian Pearson, Principal Field Applications Engineer

This presentation explores the EU Cyber Resilience Act (CRA) and its far-reaching impact on connected products entering the European market. It explains the CRA’s essential requirements, life-cycle-based security expectations, and mandatory vulnerability-management processes. The session outlines risk-based product classifications, documentation and reporting obligations, and the role of emerging horizontal and vertical standards in demonstrating compliance. It also clarifies the responsibilities for manufacturers, including support and security update requirements, and highlights how the CRA applies to both new and legacy products. Pearson will also outline how Microchip Technology is setting the benchmark for secure FPGA design, supporting customers with robust security architectures, comprehensive documentation, and proven, security-focused components—enabling faster, more confident compliance with the CRA.

Workshops

Wednesday (Day 2)

AMD logo

Agentic AI Workflows for Modern Adaptive SoC Development

Michael Hutchison, Senior Director — Customer Experience Engineering, Software, and Solutions

This hands-on workshop introduces a natural‑language-driven workflow where attendees guide an AI agent through FPGA development, from interpreting design intent to generating hardware and software artifacts.

Efinix logo

Efinity Flow with RISC-V: Program and Debug on the Eval Board

Harald Werner, VP Sales EMEA and Managing Director EMEA

A hands-on workshop that guides participants through the complete FPGA development flow using the Efinity toolchain, with a focus on integrating and debugging a RISC-V soft processor on an evaluation board.

Lattice logo

Lattice Nexus FPGA Hands-On + Agentic AI Workflow Workshop

Matt Holdsworth, Senior FAE

NEW: Introduction to Lattice Agentic AI Workflow with Radiant
Lattice Semiconductor is proud to host an in-person workshop covering our low-density Nexus range of FPGAs and introducing an agentic AI workflow for Lattice Radiant tool chain. In this session, we will work hands-on with SW tools, IPs and Development Kits to provide you with a game-changing experience for embedded applications in a wide range of market segments.

Our Partners at London 26

Platinum

AMD logo

Gold

Efinix logo
Lattice logo

Silver

Altera logo
Arrow logo
Microchip logo

Bronze

Avnet Silica logo
Eccelerators logo

Strategic

Alpha Data logo
Enclustra logo
Exostiv Labs Logo
fidus logo
Molex logo
Knowledge Resources logo
Xiphera logo
XJTAG logo

Demo partners

Adiuvo Engineering
Avnet Abacus logo
Blue Pearl AI Solutions
Chester Electronic Design
Certiqo logo
Covnetics logo
First EDA logo
Frazer-Nash logo
Future Electronics
HDL Works
iWave logo
Macnica logo
Monolithic Power Systems
MPSI
myrtle.ai logo
Nano Electronic Services
Opal Kelly logo
Opsero logo
Phoenix Semiconductor logo
PQShield logo
Renesas logo
Riverlane logo
samtec logo
Saros Technology
SemiTown
Setanta Space logo
Techway logo
Teledyne GmbH
Telexsus logo
Trenz logo

Supporting partners

EmLogic logo
Logical Branding logo
Mouser logo
Phixos logo
SGET logo
TUV logo
Pullman Hotel - exterior
Pullman Hotel - lobby
Shaw Theatre - Pullman London St Pancras

Location

Pullman London St Pancras
100 - 110 Euston Road, NW1 2AJ
LONDON